1. Field of the Invention
The present invention relates generally to overlay registration correction methods employed for fabricating microelectronic products. More particularly, the present invention relates to efficient overlay registration correction methods employed for fabricating microelectronic products.
2. Description of the Related Art
Common in the microelectronic product fabrication art is the fabrication of multiple microelectronic product types or multiple families of microelectronic product types in a single microelectronic product fabrication facility. Such pooling of microelectronic product types for fabrication within a single microelectronic product fabrication facility is particularly common in semiconductor product fabrication. Within the context of at least semiconductor product fabrication, fabrication facilities having pooled therein multiple microelectronic product types are often referred to as xe2x80x9cfoundryxe2x80x9d facilities.
While the use of foundry facilities provides for enhanced capacity utilization and thus enhanced manufacturing efficiency when fabricating microelectronic products, the use of foundry facilities is nonetheless not entirely without problems when fabricating microelectronic products.
In that regard, since foundry facilities are often employed for fabricating limited lot number quantities of large numbers of varied product types, it is often difficult to effectively predict and correct for tooling, process and design related variations which invariably arise incident to fabricating microelectronic products within foundry facilities. A particularly significant tooling, process and design related variation which arises incident to microelectronic product fabrication is a photomask overlay registration correction. Photomask overlay registration correction provides for proper alignment of successive layers when fabricating a microelectronic product.
It is thus desirable to provide within foundry facilities effective methods for providing proper photomask overlay registration.
It is towards the foregoing object that the present invention is directed.
Various methods for controlling and correcting overlay registration have been disclosed in the microelectronic product fabrication art.
Included but not limiting among the methods are methods disclosed within: (1) Ausschnitt et al., in U.S. Pat. No. 5,877,861 (a method for minimizing overlay registration error in cross-boundary stepping applications within which fields within successive levels within a microelectronic product straddle boundaries of fields within lower levels of the microelectronic product); (2) Cresswell et al., in U.S. Pat. No. 5,923,041 (an overlay registration measurement method which provides self correcting capabilities); and (3) Toprac et al., in U.S. Pat. No. 6,405,096 (an overlay registration method which provides enhanced microelectronic product overlay registration run-to-run control).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable in the microelectronic product fabrication art are additional methods for providing enhanced overlay registration control when fabricating microelectronic products, particularly within microelectronic product fabrication foundry facilities.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for controlling overlay registration when fabricating a microelectronic product within a microelectronic product fabrication facility.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the microelectronic product fabrication facility is a foundry facility.
In accord with the objects of the invention, the invention provides a method for determining an overlay registration correction for a microelectronic product fabricated within a foundry facility.
The method first provides a foundry facility having fabricated therein a plurality of microelectronic product types. The method also provides for determining for a single microelectronic product type within the plurality of microelectronic product types, and with respect to a specific alignment tool within the foundry facility, a first average historic overlay registration correction for a first pre-determined number of product lots of the single microelectronic product type previously aligned within the specific alignment tool. The method also provides for determining with respect to the specific alignment tool a second average historic overlay registration correction for a second pre-determined number of product lots of any product type previously aligned within the specific alignment tool. Finally, the method provides for introducing a new product lot of the single product type into the foundry facility and aligning the new product lot within the specific alignment tool. Within the method, an overlay registration correction for the new product lot is determined as a sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot; (2) a first factor derived from the first average historic overlay registration correction; and (3) a second factor derived from the second average historic overlay registration correction.
The present invention provides a method for controlling overlay registration when fabricating a microelectronic product within a microelectronic product fabrication facility, wherein the microelectronic product fabrication facility is a foundry facility.
The present invention realizes the foregoing object within the context of a foundry facility having fabricated therein a plurality of microelectronic product types, including a single microelectronic product type within the plurality of microelectronic product types. The invention provides for: (1) determining for the single microelectronic product type within the plurality of microelectronic product types, and with respect to a specific alignment tool within the foundry facility, a first average historic overlay registration correction for a first pre-determined number of product lots of the single microelectronic product type previously aligned within the specific alignment tool; and (2) determining with respect to the specific alignment tool a second average historic overlay registration correction for a second pre-determined number of product lots of any product type previously aligned within the specific alignment tool. Thus, within the invention, upon introducing a new product lot of the single product type into the foundry facility and aligning the new product lot within the specific alignment tool, an overlay registration correction for the new product lot may be determined as a sum of: (1) an overlay registration correction for an immediately preceding layer within the new product lot; (2) a first factor derived from the first average historic overlay registration correction; and (3) a second factor derived from the second average historic overlay registration correction.